Then the power MOSFET structure itself will be discussed, with salient features elaborated upon. The principal application of the power MOSFET (a switch) will lead to the discussion of the primary tradeoffs involved in power MOSFET design, those of breakdown voltage versus on-resistance and cutoff frequency wil be presented. The tradeoffs motivate the design of termination structures; the major types will be described.
The simulation program used, ASEPS, will be described briefly. The numerical algorithms will not be discussed in detail; rather, the equations these algorithms solve will be compared to traditional "textbook" equations and known charge distributions in actual devices to try and define the range of applicability of ASEPS to a broader class of problems than merely breakdown voltage degradation.
The degradation of power MOSFET breakdown voltage must be considered in terms of some basic parameters and processes, which will be set forth here. Differences in response of n- and p-channel response will be presented and explained, and the p-channel effects described and derived.
The results of the previous chapter will be used to understand responses of actual power MOSFETs, with an emphasis on integrated devices, since their isolation technology may adversely affect their breakdown voltage performance. To counter the effects, a new type of termination/isolation scheme is proposed and described.