RiscEmu is a processor emulator, used as a simple target architecture for entry courses in compiler construction. It was initially based on the RISC processor described by Wirth [1], almost identical to the one presented by Hennessy and Patterson [2] under the name DLX.
From the viewpoint of the programmer and the compiler designer, the computer consists of an arithmetic unit, a control unit and a store. The arithmetic unit contains 32 registers R0-R31, with 32 bits each. R0 is considered as always holding the value 0. The control unit consists of the instruction register, IR, holding the instruction currently being executed, and the program counter, PC, holding the address of the instruction to be fetched next. Branch instructions to subroutines implicitly use register R31 (LINK) to store the return address. The memory (4096 bytes) consists of 32-bit words, and it is byte-addressed, that is, word addresses are multiples of 4.
Note that the register PC holds word addresses instead of byte addresses. All the branch instruction arguments are also word addresses
| Register | Meaning |
|---|---|
R0 | 0 |
R1-R28 | GPR |
R29 | Frame Pointer (FP) |
R30 | Stack Pointer (SP) |
R31 | Link Register (LINK) |
R0 cannot be modified, SP has to be initialized by the system (at the beginning of the code).
The machine as a 4096 bytes memory. The code is loaded starting at address
0x0000.
After assembling and loading the code RiscEmu sets the PC to
0 and starts the execution.
Instructions are divided into four major categories:
The machine supports some special instructions added to provide a simple and effective way for input and output; user interaction is performed using the console (standard input and standard output).
The a and b fields are always 5 bits wide, while the c
field is 5 bits wide for register operations, 16 bits wide when used as an immediate operand and
26 bits wide when used as an absolute address.
The 16-bit field c is sign extended to 32 bits.
In the case of LSH (logical shift) and ASH (arithmetic shift) a positive
count (R.c or c) denotes a shift to the left, a negative count a shift to
the right.
The SUB and CMP instructions both form a difference.
They behave differently when the result is outside the range -231 <= x-y < 231.
Then SUB indicates arithmetic overflow, whereas CMP yields a result with the wrong
magnitude but with the correct sign.
The assembler file syntax is very simple: instructions are entered in
ASCII text (lowercase or uppercase) followed by the parameters
(blank or comma separated).
Registers are specified with their number only.
It is possible to include comments in the assembler input file in a
C-like style ( // and /* ... */ ).
/*
* Some statements
*/
addi 1 0 42 // r1 := r0 + 42 (or r1 := 42)
rd 2 // READ(r2)
mul 1 1 2 // r1 := r1 * r2
mul 1, 1, 2 // the same with commas
MUL 1 1 2 // uppercase
wrh 1 // WRITE(r1)
wrl // WRITELN()
ret 0 // terminates the program
Dowload the latest version (1.02 2002-03-05):
To install it read the INSTALL file.
Changes: ChangeLog.
RiscEmu is free and released under GPL version 2: for more information read the COPYING file.